Computers and other electronic equipment use random access memory (RAM) to store information. Often times during operation, data in one portion of memory must be written, moved or transferred to another portion. Frequently, this involves large blocks of data. A problem occurs when these transfers impact significantly on the speed with which a system performs.
Nowhere is this problem more apparent than in graphical user interface (GUI) subsystems such as computer screen displays where memory serves as a digital representation of the screen. Changing what appears on the screen involves changing the data in the memory array.
Oftentimes, certain images on the screen are merely being copied from one location in memory and written to another. A bit-block transfer (BitBLT).operation accomplishes the necessary change in memory by reading data from one location of a memory array, and then writing it to another location. Current personal computer software applications such as Microsoft's WINDOWS make extensive use of these types of transfers.
A typical subsystem might serve a screen of 1024.times.768 pixels, each of which might be represented in memory as an 8-bit color/intensity value. Pixels can in turn be grouped into pixel words, depending on the system architecture. For instance, in a 32-bit machine, four 8-bit pixels may be conveniently grouped into one 32-bit pixel word.
For example, a computer screen is divided into an array or grid of pixels, 768 rows by 1024 columns. The information concerning the color/intensity for each pixel at a given time is stored in a RAM array frame buffer, as shown in FIG. 1, where 8-bit pixels are grouped into pixel-words having 4 pixels per pixel-word.
FIG. 2 shows the upper left portion of the frame buffer memory array wherein each pixel-word is composed of four pixels in adjacent columns. Suppose we wish to transfer pixels C-J from their current position in row 0 to a destination in row 3. Since the architecture deals in pixel-words, a potential problem occurs when the source address of a pixel falls in a different position within a pixel-word than does the destination address. In this case, pixel C shifts from position 2 in its source pixel-word to position 1 in its destination pixel-word.
Another potential problem occurs when the location of the beginning or ending pixel in a block of pixels to be transferred is not on a pixel-word boundary. When the number of pixels being transferred is not divisible evenly by four (i.e. not modulo 4), some part of the block, either the beginning or the end or both, will not fall cleanly on a pixel-word boundary.
The subsystem architecture must be designed to handle all the possible situations which can arise when a block of data to be transferred is not aligned cleanly on pixel-word boundaries. The more complex data manipulations required for these unaligned BitBLT's can further sap system resources.
Since BitBLT's are a significant factor in overall GUI subsystem performance, increasing their speed improves the system.
Current solutions to the problem include the development of several coprocessed graphics cards having a block transfer engine such as the 8514A and XGA, both developed by IBM, Inc., and the S3 Accelerator, developed by S3, Inc.
These solutions utilize only a single port into the RAM array, and therefore both read and write access operations must occur through that port. It would be advantageous to have an architecture which might utilize more than one port in performing memory access operations.